EEG Machine Testing Standards: IEC 80601-2-26:2019

The basic electrical performance test specifications for electroencephalographs are found in sections 201.12.1.101 to 106 of the IEC 80601-2-26:2019 standard.

The basic electrical performance tests specified in the EEG standard mainly include tests of electrical performance. The test methods are divided into two main categories: one category asks to generate the required test signals based on the general test circuit diagram attached to the standard to test the electrical performance of the EEG machine; the other category ask to generate the required test signals based on the CMRR (Common Mode Rejection Ratio) circuit diagram attached to the standard to test the CMRR and internal noise level of the EEG machine. Table 1 provides an overall overview of each test item, the relevant standard section, and the main performance characteristics to be verified .

Table 1 : Test Items and Key Performance Validation Requirements in Chapter 201.12.1 of IEC 80601-2-26 :2019

Test Items in IEC Standards

The main specifications are detailed in section 201.12.1, "Accuracy of Instruments and Controls ," which includes items tested using a general test circuit and items tested using a common-mode rejection ratio (CMRR) circuit. These are described in detail below:

1. General Test Circuit

This circuit is characterized by single-channel testing. As shown in Figure 1, the signal generator on the left generates the test signal required by the standard. After passing through a 500 : 1 voltage divider (50KΩ:100Ω), the positive terminal of the voltage, attenuated by 500 times, is sent to the electrode under test (in the example in Figure 1, this is to the CHANNEL 1 electrode) via P1 . All other electrodes are connected to the negative terminal of the signal generator via P2. The path to the electrode under test also includes the superposition of a ±150 mV DC offset voltage controlled by an Sdc switch .

The positive and negative signals generated by the signal generator are connected to the positive (P1) and negative (P2) terminals of CHANNEL 1 on the EEG under test, only the CHANNEL 1 waveform is displayed on the EEG under test . This method of testing a single channel by passing the signal through a single electrode of the channel under test is called single-channel testing. Therefore, a single-channel tester must be used during testing .

Figure 1: General Test Circuit

The main test items in IEC 80601-2-26 :2019 include:
1.1 201.12.1.101 Scale and calibration signal
not require testing. It only requires a scale and calibration signal displayed in mV or μV on the EEG under test . It does not require testing with a single-channel tester; visual inspection is sufficient.

1.2 201.12.1.102 Accuracy of amplitude and rate of variation
Tests are performed on the scalp and /or the cerebral cortex or subdural region . Two different EEG methods ( or subdural locations ) are used, but the amplitudes differ. The test signal is a 6 Hz triangular wave with amplitudes of 1 mV, 0.5 mV, 0.2 mV, and 0.1 mV for the scalp, and 20 mV, 10 mV, 4 mV, and 2 mV for the cortex or subdural locations . The amplitude error should be ≤ ±20% of the nominal output value or ±10 μV, whichever is greater.

1.3 201.12.1.103 Input dynamic range and differential offset voltage
This test primarily uses a ±150 mV DC differential bias voltage to measure the dynamic range of the EEG under test. The test signal is a triangular wave , 6 Hz, 1 mV. After adding a ±150 mV DC bias , the change in output signal amplitude must not exceed ±10%. Then, by changing the added -150 mV DC bias, the change in output signal amplitude must not exceed ±10% .

1.4 201.12.1.105 Frequency response
test from 0.5 Hz to 50 Hz. The 50/60 Hz notch filter and any other filters must be turned off during testing. The test signal is a sine wave, 50 μV . First, set the frequency to 5 Hz , then measure the amplitude displayed on the EEG under test. Next, adjust the test signal frequency to 0.5 Hz , then 50 Hz. Compare the amplitudes measured at 0.5 Hz and 50 Hz with the amplitude at 5 Hz; the error should be between 71 % and 110%.

2. CMRR and Input Noise

As shown in Figure 2, the signal generator on the left generates the test signal required by the standard. This signal passes through a 200 pF line consisting of C1, Ct, and Cx connected in parallel to point B, called the Common Mode Point. Next is the S0 switch; S0 is closed for all CMRR tests, only opening during input noise testing. After the S0 switch, all electrode wires of the EEG machine under test are connected in series with a 10 kΩ parallel 47 nF analog electrode skin impedance line, and then all are short-circuited to the Common Mode Point. All 10 kΩ parallel 47 nF lines are controlled by switches S1 to Sn and SR to determine whether each electrode is connected in series with this impedance line. Additionally, the electrode under test, in the example of CHANNEL 1 in Figure 2 , can also be controlled by the SR DC switch to determine whether a ± 150 mV DC bias voltage is applied. The two dashed boxes in the diagram represent the inner and outer shield facilities. There will be a parasitic capacitance Cx between the two shields . Therefore, an adjustable capacitor Ct is used to adjust the source impedance to Ct + Cx = 100 pF plus C1 = 100 pF, for a total of 200 pF .

Figure 2: CMRR and Input Noise Test Circuit

2.1 201.12.1.105 The CMRR test mainly includes the following 5 steps
The signal generator produces the test signal required by the standard, IEC80601-2-2 6, which requires a 2 Vrms power supply frequency (50 Hz or 60 Hz) signal voltage (Vs).
If the EEG under test has a 50/60 Hz power supply notch filter , it must be turned off .
With all EUT electrode lines disconnected, adjust the adjustable capacitor Ct until the common-mode point voltage (Vc) is half the power supply frequency signal voltage (Vs). This step is mainly to determine that Ct + Cx = 100 pF.
Connect all electrode wires to the EUT and perform an imbalance test . According to the standard settings, only open the Sn switch of the electrode under test and close all other Sn switches . Then measure the waveform amplitude of all channels . All amplitudes must not exceed 100 μVp-v.
A ±150 mV DC bias voltage is sequentially superimposed on the electrode circuit under test, and the waveform amplitude of all channels is measured . The amplitude of all channels must not exceed 100 μVp-v.

2.2 201.12.1.1 04 Input Noise Test
Connect all EUT electrode leads to the CMRR tester. Turn S0 ON to disable and isolate the power line, enable the 50/60 Hz power frequency notch filter, and set switches S1 through Sn to OFF (closed). Measure the waveform amplitude of all channels. The waveform amplitude of each channel shall not exceed 6 µVp-v.

EEG Testers for IEC 80601-2-26 Compliance

According to the basic electrical performance requirements of EEG standards, an EEG testing device should include a single-channel tester and a CMRR tester. These testers generate test signals to the EEG under test by connecting electrodes to each channel . A schematic diagram of the connection system is shown in Figure 3. Since EEG signals are as small as mV or µV, they are easily affected by ambient noise, especially power frequency noise. Therefore, it is best to place the tester and the EEG under test on the metal plate shown in Figure 3 and connect the grounding point to the metal plate. This metal plate serves as a self-made reference ground (GND), which can effectively reduce noise interference. Furthermore, control software can more easily control the tester settings, and a software development kit (SDK) can be used to control the tester for customized automated testing.

 
Figure 3: Schematic diagram of the EEG testing system connected to DUT

1. Single-Channel Tester

The single-channel tester mainly performs basic electrical performance tests based on the general test circuit shown in Figure 1. In addition to meeting all the accuracy requirements of the standard, because there are many test items, in order to make the test more convenient, faster and more complete, the single-channel tester uses a microprocessor to control some electronic relays and various standard signal sources without violating the spirit of the general test circuit and eliminating internal noise interference. This allows the tester to easily and quickly set the test conditions required for the test items.

Figure 4 shows the control software window of a single-channel tester, which includes the signal types, parameter ranges, and switch options required by the EEG standard for single-channel testing. Some of the settings in the red boxes in the figure are examples of the input dynamic range and differential bias voltage test (201.12.1.103). The test parameters are a 1 mV, 6 Hz triangular wave output from the single-channel tester to Channel 1 , then superimposed with a +150 mV DC bias to Channel 1. These parameters only need to be set once in the control software before testing can begin.

Figure 4 : Control software window of the single-channel tester, containing all signal types, parameter settings, and on/off options required for single-channel testing.

This type of tester, which uses software to control the settings, can also use an SDK to control the parameter setting steps of the tester. In this way, test steps for each EEG standard's single-channel test item can be programmed individually for automated testing. The Assistant in the lower right corner of Figure 4 is an auxiliary program written according to the IEC standard. As shown in Figure 5 , the selected test item is the input dynamic range and differential bias voltage of IEC 80601-2-2 6 Chapter 103 201.12.1.103. The tester only needs to select the test steps, without needing to select test signals, parameters, switches, and other complex options, saving the tester a significant amount of testing time.

The test steps are shown in the central part of Figure 5. The tester only needs to select the output channel and test conditions (whether to add a ± 150 mV DC bias ). The pass criteria are also listed in Pass Criterion. Detailed test steps will be listed after pressing the Test Sequence button for reference during testing. After pressing Run, the software will control the single-channel tester to generate the test signals, parameters, and switches required for the test according to the selected test conditions.

Figure 5 : IEC 80601-2-26 Assistant software window of the single-channel tester

2. Common Mode Rejection Ratio Tester

The common-mode rejection tester primarily performs basic electrical performance tests based on the common-mode rejection ratio and input noise circuitry shown in Figure 2. Similar to single-channel testers, in addition to meeting all accuracy requirements of the standards, it also uses a microprocessor to control electronic relays and power signal sources. This allows the tester to easily and quickly set the necessary test conditions for the test items . More importantly, the tester's design must meet the five main functions required by the standards , namely:

1. The signal generator must be able to generate a power frequency signal of at least 2 Vrms (Vs) .
2. A power signal of 50 Hz or 60 Hz can be selected.
3. The value of the adjustable capacitor Ct can be adjusted until Vc is half of the power supply frequency signal voltage value Vs.
4. on or off the electrode under test.
5. A DC bias voltage of ±150 mV is applied .

Figure 6 shows the control software window of a common-mode rejection tester. All parameter settings are designed for the five main functions required by the IEC 80601-2-26:2019 standard, including:

1. Supply Voltage (Vs): Set the effective voltage value to 2.0 Vrms.
2. Frequency: Set the supply voltage frequency to 50/60 Hz.
3. Inner shield (Vc): Adjust the Ct value until Vc is half the supply voltage Vs (1 Vrms) .
4. Electrode with Impedance ( 10 KΩ/47nF parallel circuit ): Controls the opening or closing of the Sn switch on the electrode under test .
5. DC Offset : Select whether to add a ± 150 mV DC offset to the electrode under test, including OF , +150 , and -150 . (where RA/LA/LL/V1~V6 can be represented as CH1~CH9)

 
Figure 6 : Control software window of the common-mode rejection tester, containing all the signal types and parameter settings required for the test.

During common-mode rejection testing, the tester should maintain a certain distance from the test system to avoid the capacitive effect caused by proximity affecting the test results. If a capacitive effect does occur due to proximity, the tester can touch the metal plate that is grounded to the system to minimize the impact.

Differences between IEC 80601-2-26:2019 and IEC 60601-2-26:2012

between the 2019 and 2012 versions of the EEG standard lie in changes to both the general testing circuitry and the CMRR testing circuitry. The main differences are a reduced DC bias voltage and the elimination of the series resistor for each lead , among others. For detailed differences, please refer to Table 2. Due to the reduced DC voltage, the CMRR series impedance has decreased from 5.1KΩ to 10KΩ. These changes lower the electrical performance requirements for the EEG machine. Of course, if the testing requirements of the old standard must be followed, both general-purpose and CMRR testers must be modified internally to meet the testing requirements.

Table 2: Differences between IEC 80601-2-26:2019 and IEC 60601-2-26:2012

Conclusion: Electrical Performance Testing According to Current IEC Standards

Basic electrical performance tests for EEG machines primarily aim to provide methods for enabling the machine to completely capture brain signals and accurately display brain waves . Therefore, it's best to include the specifications required for these tests in the initial design phase of each type of EEG machine. The R&D process should naturally follow these requirements to progressively complete the product design. Final quality verification and production line testing can then be conducted one by one, or by selecting key items, based on these requirements. Since these standard tests provide the electrical specifications for various types of EEG machines, it is essential for EEG machine manufacturers, from the initial design phase to the final production line testing, for all personnel involved to understand the entire testing framework and its spirit. This will prevent them from falling into the predicament of repeatedly modifying product lines and specifications.

Of course, fully understanding the entire standard is a time-consuming task. Therefore, if EEG testing device manufacturers can present all testing steps in an automated manner, it will greatly help engineers save a lot of time in understanding and testing. The two testing devices introduced above, in addition to meeting the functions required by the standard, basically include software for automating testing steps. Furthermore, they also provide SDK functionality to control the testing device for customized automated testing. This can help EEG machine manufacturers bring their products to market sooner, allowing engineers to focus more on the research and development of the EEG machine itself, developing EEG machines with superior quality and functionality.

Next-Generation EEG Testing, an Urgent Need for New Standards

With the rapid development of BCI (Brain-Computer Interface) technology, research on brain waves will inevitably become more precise and extensive. IEC80601-2-26:2019, while increasing the test signal amplitude to 20 mV, does not address the performance testing of the BCI interface itself. Furthermore, the addition of stimulation signals for closed-loop testing of EEG machines is a currently popular development, but there are no standards for functional testing of these devices. Therefore, developing new standards to meet the functional requirements of these new applications is an urgent issue.

Algorithms for automatically identifying EEG symptoms are also an important trend in the development of EEG applications. Therefore, a sufficient database of standard EEG symptoms is crucial foundational data. Sufficient data is needed to train the algorithm, leading to more accurate calculation results and increasing its reliability.

For the aforementioned BCI EEG, new testing devices must be designed to verify the addition of closed-loop EEG with stimulation signals , EEG that automatically identifies EEG disorders , and other new functions.

‒    New test equipment – a multi-channel tester and an oscilloscope-like receiver :

Closed-loop EEG testing: The new testing device requires a multi-channel setup to generate EEG waveforms for certain conditions and feed them to the EEG sample. An oscilloscope-like receiver is then used to measure and determine the parameters of the stimulus signal. Finally, another set of EEG waveforms is played back to the EEG sample via the multi-channel testing device , completing the closed-loop test. Therefore, closed-loop testing requires both a multi-channel testing device and a receiver to play back the EEG waveforms and measure the stimulus signal parameters .

Automatically identify EEG disorders: requires the use of a multi-channel tester to simultaneously play EEG waveforms from a standard database of multiple channels. Since the number of channels in an EEG can be as high as 256 , designing the number of channels in a multi-channel tester is a significant challenge.

References

1. IEC Medical Standard IEC 80601-2-2 6 :201 9 .
2. IEC Medical Standard IEC 60601-2-2 6 :201 2.
3. WhaleTeq SEEG 100E, CMRR 3.0E User Manual.